During the past fifty years, the electronics and computing industries have been relentlessly propelled forward by ever decreasing sizes of basic electronic components, such as transistors and signal lines, and by correspondingly ever increasing component densities of integrated circuits, including processors and electronic memory chips. Eventually, however, it is expected that fundamental component-size limits will be reached in semiconductor-circuit-fabrication technologies based on photolithographic methods. As the size of components decreases below the resolution limit of ultraviolet light, for example, far more technically demanding and expensive higher-energy-radiation-based technologies may need to be employed to create smaller components using photolithographic techniques. Expensive semiconductor fabrication facilities may need to be rebuilt in order to use the new techniques. Many new obstacles are also expected to be encountered. For example, it is necessary to fabricate semiconductor devices through a series of photolithographic steps, with precise alignment of the masks used in each step with respect to the components already fabricated on the surface of a nascent semiconductor. As the component sizes decrease, precise alignment becomes more and more difficult and expensive. As another example, the probabilities that certain types of randomly distributed defects in semiconductor surfaces result in defective semiconductor devices may increase as the sizes of components manufactured on the semiconductor surfaces decrease, resulting in an increasing proportion of defective devices during manufacture, and a correspondingly lower yield of useful product. Ultimately, various quantum effects that arise only at molecular-scale distances may altogether overwhelm current approaches to component fabrication in semiconductors.
In view of these problems, researchers and developers have expended considerable research effort in fabricating sub-microscale and nanoscale electronic devices using alternative technologies. Nanoscale electronic devices generally employ nanoscale signal lines having widths, and nanoscale components having dimensions, of less than 100 nanometers. More densely fabricated nanoscale electronic devices may employ nanoscale signal lines having widths, and nanoscale components having dimensions, of less than 50 nanometers, and, in certain types of devices, less than 10 nanometers. A nanoscale electronic device may include sub-microscale, microscale, and larger signal lines and components.
Although general nanowire technologies have been developed, it is not necessarily straightforward to employ nanowire technologies to miniaturize existing types of circuits and structures. While it may be possible to tediously construct miniaturized, nanowire circuits similar to the much larger, current circuits, it is impractical, and often impossible, to manufacture such miniaturized circuits using current technologies. Even were such straightforwardly miniaturized circuits able to be feasibly manufactured, the much higher component densities that ensue from combining together nanoscale components necessitate much different strategies related to removing waste heat produced by the circuits. In addition, the electronic properties of substances may change dramatically at nanoscale dimensions, so that different types of approaches and substances may need to be employed for fabricating even relatively simple, well-known circuits and subsystems at nanoscale dimensions. Thus, new implementation strategies and techniques need to be employed to develop and manufacture useful circuits and structures at nanoscale dimensions using nanowires.
Designers and manufacturers of nanoscale electronic devices have recently begun implementing multiplexer/demultiplexer circuits at the nanoscale level. One possible use for multiplexer/demultiplexer circuits is for interfacing signal nanowires with microscale or sub-microscale address lines. The number of address lines needed to uniquely address each of M nanowire signal lines with a high degree of probability in current nanoscale multiplexer/demultiplexer circuits implemented using randomly fabricated interconnections is k log2 M, where k is a value that represents an increase in the number of address lines needed for nanoscale multiplexer/demultiplexer circuits using randomly fabricated interconnections over the number of address lines needed for nanoscale multiplexer/demultiplexer circuits using non-randomly, or deterministically fabricated interconnections. For nanoscale multiplexer/demultiplexer circuits with significant line-gauge differences, it is often advantageous to employ small numbers of microscale or sub-microscale address lines. Designers, manufacturers, and users of electrical systems integrating nanowires within microscale or sub-microscale electronic devices have, therefore, recognized the need for decreasing the number of microscale or sub-microscale address lines used to uniquely address M nanowires of a nanoscale electronic device using random interconnections.